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7.5.4 MCU1 Development Guide

MCU Interrupt Number and Module Correspondence​

ModuleInterrupt NumberName
SGI0~15
PPI16~31
MCU_STCU32Bist_Stcu0Isr
MEDIA_TOP_STCU33Bist_Stcu1Isr
VIDEO_STCU34Bist_Stcu2Isr
VDSP_STCU35Bist_Stcu3Isr
HSIS_STCU36Bist_Stcu4Isr
GPU_STCU37Bist_Stcu5Isr
DDR2_STCU38Bist_Stcu6Isr
DDR1_STCU39Bist_Stcu7Isr
DDR0_STCU40Bist_Stcu8Isr
CPU_MP4_STCU41Bist_Stcu9Isr
CPU_MP2_STCU42Bist_Stcu10Isr
CAM_STCU43Bist_Stcu11Isr
BPU0_STCU44Bist_Stcu12Isr
UART045Uart0_Isr
UART146Uart1_Isr
UART247Uart2_Isr
ADC048Adc_Ch0WdIsr
49Adc_Ch1WdIsr
50Adc_Ch2WdIsr
51Adc_Ch3WdIsr
52Adc_Ch4WdIsr
53Adc_Ch5WdIsr
54Adc_Ch6WdIsr
55Adc_Ch7WdIsr
56Adc_Ch8WdIsr
57Adc_Ch9WdIsr
58Adc_Ch10WdIsr
59Adc_Ch11WdIsr
60Adc_Ch12WdIsr
61Adc_Ch13WdIsr
62Adc_InjIsr
63Adc_NorIsr
I2C064I2c0_Isr
I2C165I2c1_Isr
I2C266I2c2_Isr
I2C367I2c3_Isr
GPIO068Gpio_Icu0ExtIsr
GPIO169Gpio_Icu1ExtIsr
GPIO270Gpio_Icu2ExtIsr
WWDT071Wdg_Ins0RstIsr
72Wdg_Ins0IntIsr
WWDT173Wdg_Ins1RstIsr
74Wdg_Ins1IntIsr
WWDT275Wdg_Ins2RstIsr
76Wdg_Ins2IntIsr
OTF_CRC077Otf_Isr
CRC078Crc_Isr
GPT079Gpt_Ins0Ch0Isr
80Gpt_Ins0Ch1Isr
81Gpt_Ins0Ch2Isr
82Gpt_Ins0Ch3Isr
GPT183Gpt_Ins1Ch0Isr
84Gpt_Ins1Ch1Isr
85Gpt_Ins1Ch2Isr
86Gpt_Ins1Ch3Isr
GPT287Gpt_Ins2Ch0Isr
88Gpt_Ins2Ch1Isr
89Gpt_Ins2Ch2Isr
90Gpt_Ins2Ch3Isr
GPT391Gpt_Ins3Ch0Isr
92Gpt_Ins3Ch1Isr
93Gpt_Ins3Ch2Isr
94Gpt_Ins3Ch3Isr
GPT495Gpt_Ins4Ch0Isr
96Gpt_Ins4Ch1Isr
97Gpt_Ins4Ch2Isr
98Gpt_Ins4Ch3Isr
GPT599Gpt_Ins5Ch0Isr
100Gpt_Ins5Ch1Isr
101Gpt_Ins5Ch2Isr
102Gpt_Ins5Ch3Isr
PMU103Pmu_ReqDeny0Isr
BIFSPI104
PVT105Pvt_McuAlarmIsr
L1FCHM106Fchm_MissionIntIsr
107Fchm_NcfIntIsr
108Fchm_CfIntIsr
CMM0109Cmm_Ins0Isr
CMM1110Cmm_Ins1Isr
PWM0111Pwm_Generic0Isr
XSPI112Xspi_Isr
CANFD0113Can0_TimestampIsr
114Can0_WakeupIsr
115Can0_ErrorIsr
116Can0_DataIsr
CANFD1117Can1_TimestampIsr
118Can1_WakeupIsr
119Can1_ErrorIsr
120Can1_DataIsr
CANFD2121Can2_TimestampIsr
122Can2_WakeupIsr
123Can2_ErrorIsr
124Can2_DataIsr
CANFD3125Can3_TimestampIsr
126Can3_WakeupIsr
127Can3_ErrorIsr
128Can3_DataIsr
CANFD4129Can4_TimestampIsr
130Can4_WakeupIsr
131Can4_ErrorIsr
132Can4_DataIsr
CANFD5133Can5_TimestampIsr
134Can5_WakeupIsr
135Can5_ErrorIsr
136Can5_DataIsr
CANFD6137Can6_TimestampIsr
138Can6_WakeupIsr
139Can6_ErrorIsr
140Can6_DataIsr
CANFD7141Can7_TimestampIsr
142Can7_WakeupIsr
143Can7_ErrorIsr
144Can7_DataIsr
CANFD8145Can8_TimestampIsr
146Can8_WakeupIsr
147Can8_ErrorIsr
148Can8_DataIsr
CANFD9149Can9_TimestampIsr
150Can9_WakeupIsr
151Can9_ErrorIsr
152Can9_DataIsr
mcu eth153Gmac_TxCh0Isr
154Gmac_TxCh1Isr
155Gmac_TxCh2Isr
156Gmac_TxCh3Isr
157Gmac_TxCh4Isr
158Gmac_TxCh5Isr
159Gmac_RxCh0Isr
160Gmac_RxCh1Isr
161Gmac_RxCh2Isr
162Gmac_RxCh3Isr
163Gmac_RxCh4Isr
164Gmac_RxCh5Isr
165Gmac_SbdIsr
166Gmac_PmtIsr
167Gmac_LpiIsr
LIN0168Lin0_Isr
LIN1169Lin1_Isr
LIN2170Lin2_Isr
SPI0171Spi0_Isr
SPI1172Spi1_Isr
SPI2173Spi2_Isr
SPI3174Spi3_Isr
SPI4175Spi4_Isr
SPI5176Spi5_Isr
IPC177Ipc_Ch0Isr
178Ipc_Ch1Isr
179Ipc_Ch2Isr
180Ipc_Ch3Isr
181Ipc_Ch4Isr
182Ipc_Ch5Isr
183Ipc_Ch6Isr
184Ipc_Ch7Isr
185Ipc_Ch8Isr
186Ipc_Ch9Isr
187Ipc_Ch10Isr
188Ipc_Ch11Isr
189Ipc_Ch12Isr
190Ipc_Ch13Isr
191Ipc_Ch14Isr
192Ipc_Ch15Isr
193Ipc_Ch16Isr
194Ipc_Ch17Isr
195Ipc_Ch18Isr
196Ipc_Ch19Isr
197Ipc_Ch20Isr
198Ipc_Ch21Isr
199Ipc_Ch22Isr
200Ipc_Ch23Isr
201Ipc_Ch24Isr
202Ipc_Ch25Isr
203Ipc_Ch26Isr
204Ipc_Ch27Isr
205Ipc_Ch28Isr
206Ipc_Ch29Isr
207Ipc_Ch30Isr
208Ipc_Ch31Isr
MDMA0209Mdma0_Ch0Isr
210Mdma0_Ch1Isr
MDMA1211Mdma1_Ch0Isr
212Mdma1_Ch1Isr
PDMA0213PDMA0_Ch0Isr
214PDMA0_Ch1Isr
215PDMA0_Ch2Isr
216PDMA0_Ch3Isr
217PDMA0_Ch4Isr
218PDMA0_Ch5Isr
PMC0219Pmc0_Isr
PMC1220Pmc1_Isr
PPS(RTC)221Pps_IcuRtcIsr
PPS(TIME_SYNC0)222Pps_Icu0Isr
PPS(TIME_SYNC1)223Pps_Icu1Isr
PPS(TIME_SYNC2)224Pps_Icu2Isr
PPS_SYNC225Pps0_Isr
226Pps1_Isr
227Pps2_Isr
228Pps3_Isr
229Pps4_Isr
HSM_IPC0230Ipc_HsmIpc0Ch4Isr
231Ipc_HsmIpc0Ch5Isr
232Ipc_HsmIpc0Ch6Isr
233Ipc_HsmIpc0Ch7Isr
Reserved234
235
236
237
238
239
240
HSM_IPC1241Ipc_HsmIpc1Ch4Isr
242Ipc_HsmIpc1Ch5Isr
243Ipc_HsmIpc1Ch6Isr
244Ipc_HsmIpc1Ch7Isr
CPU_MP4_CMM245Cmm_Ins13Isr
CPU_MP4_CLUSTER_PMU246Pmu_ReqDeny1Isr
CPU_MP4_CDB_PMU247Pmu_ReqDeny2Isr
CPU_MP2_CMM248Cmm_Ins14Isr
CPU_MP2_CLUSTER_PMU249Pmu_ReqDeny3Isr
CPU_MP2_CDB_PMU250Pmu_ReqDeny4Isr
CPU_IPC1_CH0251Ipc_CpuIpc1Ch0Isr
CPU_IPC1_CH1252Ipc_CpuIpc1Ch1Isr
CPU_IPC1_CH2253Ipc_CpuIpc1Ch2Isr
CPU_IPC0_CH0254Ipc_CpuIpc0Ch0Isr
CPU_IPC0_CH1255Ipc_CpuIpc0Ch1Isr
CPU_IPC0_CH2256Ipc_CpuIpc0Ch2Isr
CPU_IPC0_CH3257Ipc_CpuIpc0Ch3Isr
CPU_IPC0_CH4258Ipc_CpuIpc0Ch4Isr
CPU_IPC0_CH5259Ipc_CpuIpc0Ch5Isr
CPU_IPC0_CH6260Ipc_CpuIpc0Ch6Isr
CPU_IPC0_CH7261Ipc_CpuIpc0Ch7Isr
CPU_IPC0_CH8262Ipc_CpuIpc0Ch8Isr
CPU_IPC0_CH9263Ipc_CpuIpc0Ch9Isr
CPU_IPC0_CH10264Ipc_CpuIpc0Ch10Isr
CPU_IPC0_CH11265Ipc_CpuIpc0Ch11Isr
CPU_IPC0_CH12266Ipc_CpuIpc0Ch12Isr
CPU_IPC0_CH13267Ipc_CpuIpc0Ch13Isr
CPU_IPC0_CH14268Ipc_CpuIpc0Ch14Isr
CPU_IPC0_CH15269Ipc_CpuIpc0Ch15Isr
CPU_ROUTER_SWTRIG1_0270Router_Swtrig1Ch0Isr
CPU_ROUTER_SWTRIG1_1271Router_Swtrig1Ch1Isr
CPU_ROUTER_SWTRIG1_2272Router_Swtrig1Ch2Isr
CPU_ROUTER_SWTRIG1_3273Router_Swtrig1Ch3Isr
DDR0_CMM291Cmm_Ins2Isr
DDR1_CMM294Cmm_Ins3Isr
DDR2_CMM297Cmm_Ins4Isr
PERI_I2C0300Peri_I2C0Isr
PERI_I2C1301Peri_I2C1Isr
PERI_I2C2302Peri_I2C2Isr
PERI_I2C3303Peri_I2C3Isr
PERI_I2C4304Peri_I2C4Isr
PERI_I2C5305Peri_I2C5Isr
PERI_USB306Peri_UsbIsr
PERI_CMM307Cmm_Ins19Isr
CAM_ISP0_0308Cam_Isp0Ch0Isr
CAM_ISP0_1309Cam_Isp0Ch1Isr
CAM_ISP0_2310Cam_Isp0Ch2Isr
CAM_ISP0_3311Cam_Isp0Ch3Isr
CAM_CPE0_PYM312Cam_Cpe0PymIsr
CAM_CPE0_MIPI_RX_CSI313Cam_Cpe0MipiRxCsiIsr
CAM_CPE0_CIM314Cam_Cpe0CimIsr
CAM_CPE0_PYM_PRE_UV315Cam_Cpe0PymPreUvIsr
CAM_CPE0_PYM_PRE_Y316Cam_Cpe0PymPreYIsr
CAM_CPE0_CMM317Cmm_Ins8Isr
CAM_ISP1_0318Cam_Isp1Ch0Isr
CAM_ISP1_1319Cam_Isp1Ch1Isr
CAM_ISP1_2320Cam_Isp1Ch2Isr
CAM_ISP1_3321Cam_Isp1Ch3Isr
CAM_CPE1_YNR322Cam_Cpe1YnrIsr
CAM_CPE1_PYM323Cam_Cpe1PymIsr
CAM_CPE1_MIPI_RX_CSI324Cam_Cpe1MipiRxCsiIsr
CAM_CPE1_CIM325Cam_Cpe1CimIsr
CAM_CPE1_PYM_PRE_UV326Cam_Cpe1PymPreUvIsr
CAM_CPE1_PYM_PRE_Y327Cam_Cpe1PymPreYIsr
CAM_CPE1_CMM328Cmm_Ins7Isr
CAM_STITCH329Cam_StichIsr
CAM_CPE_LITE_MIPI_RX330Cam_CpeLiteMipiRxCsiIsr
CAM_GDC0331Cam_Gdc0Isr
CAM_CPE_LITE_PYM332Cam_CpeLitePymIsr
CAM_CPE_LITE_PYM_PRE_UV333Cam_CpeLitePymPreUvIsr
CAM_CPE_LITE_PYM_PRE_Y334Cam_CpeLitePymPreYIsr
CAM_CPE_LITE_CIM335Cam_CpeLiteCymIsr
CAM_CPE_LITE_CMM336Cmm_Ins6Isr
CAM_MIPI_TX1_DSI337Cam_MipiTx1DsiIsr
CAM_MIPI_TX1_CSI2338Cam_MipiTx1Csi2Isr
CAM_MIPI_TX0_DSI339Cam_MipiTx0DsiIsr
CAM_MIPI_TX0_CSI2340Cam_MipiTx0Csi2Isr
CAM_IDU0341Cam_Idu0Isr
CAM_IDU1342Cam_Idu1Isr
CAM_IDE_CMM343Cmm_Ins5Isr
CAM_GPIO344Cam_GpioIsr
CAM_TOP_CMM345Cmm_Ins9Isr
VIDEO_VPU346Vid_VpuIsr
VIDEO_JPU347Vid_JpuIsr
VIDEO_CMM348Cmm_Ins10Isr
VIDEO_GIPO349Vid_GpioIsr
VDSP_CMM350Cmm_Ins11Isr
VDSP_Q8_EARLY_REST351Vdsp_EarlyRestIsr
VDSP_Q8_REST352Vdsp_ResetIsr
HSIS_CMM353Cmm_Ins12Isr
BPU_VM0354Bpu_Vm0Isr
BPU_VM1355Bpu_Vm1Isr
BPU_HYP356Bpu_HypIsr
BPU_PVT357Pvt_BpuAlarmIsr
BPU_CMM358Cmm_Ins17Isr
GPU_CMM359Cmm_Ins18Isr
RTC360Rtc_Isr
AON_WAKEUP_GPIO361Aon_WakeUpGpioIsr
AON_GPIO362Aon_GpioIsr
AON_PMU_REQ_MOD363Aon_PmuReqModIsr
MEDIA_BOT_CMM364Cmm_Ins15Isr
MEDIA_TOP_CMM366Cmm_Ins16Isr
CMN_CMM368Cmm_Ins20Isr
CMN_PVTC369Pvt_CmnAlarmIsr
CMN_PPU_PMU370Pmu_Ppu0Isr
ModuleInterrupt NumberName
SGI0~15
PPI16~31
MCU_STCU32Bist_Stcu0Isr
PERI_STCU33Bist_Stcu1Isr
VIDEO_STCU34Bist_Stcu2Isr
VDSP0_STCU35Bist_Stcu3Isr
VDSP1_STCU36Bist_Stcu4Isr
HSIS_STCU37Bist_Stcu5Isr
GPU_STCU38Bist_Stcu6Isr
DDR0_STCU39Bist_Stcu7Isr
DDR1_STCU40Bist_Stcu8Isr
DDR2_STCU41Bist_Stcu9Isr
DDR3_STCU42Bist_Stcu10Isr
MP4_0_STCU43Bist_Stcu11Isr
MP4_1_STCU44Bist_Stcu12Isr
MP4_2_STCU45Bist_Stcu13Isr
MP4_3_STCU46Bist_Stcu14Isr
MP2_4_STCU47Bist_Stcu15Isr
CAM_STCU48Bist_Stcu16Isr
BPU0_STCU49Bist_Stcu17Isr
BPU1_STCU50Bist_Stcu18Isr
BPU2_STCU51Bist_Stcu19Isr
BPU3_STCU52Bist_Stcu20Isr
SRAM0_STCU53Bist_Stcu21Isr
SRAM1_STCU54Bist_Stcu22Isr
SRAM2_STCU55Bist_Stcu23Isr
SRAM3_STCU56Bist_Stcu24Isr
RESERVED57
RESERVED58
RESERVED59
UART060Uart0_Isr
UART161Uart1_Isr
UART262Uart2_Isr
UART363Uart3_Isr
ADC064Adc0_Ch0WdIsr
65Adc0_Ch1WdIsr
66Adc0_Ch2WdIsr
67Adc0_Ch3WdIsr
68Adc0_Ch4WdIsr
69Adc0_Ch5WdIsr
70Adc0_Ch6WdIsr
71Adc0_Ch7WdIsr
72Adc0_InjIsr
73Adc0_NorIsr
ADC174Adc1_Ch0WdIsr
75Adc1_Ch1WdIsr
76Adc1_Ch2WdIsr
77Adc1_Ch3WdIsr
78Adc1_Ch4WdIsr
79Adc1_Ch5WdIsr
80Adc1_Ch6WdIsr
81Adc1_Ch7WdIsr
82Adc1_InjIsr
83Adc1_NorIsr
I2C084I2c0_Isr
I2C185I2c1_Isr
I2C286I2c2_Isr
I2C387I2c3_Isr
I2C488I2c4_Isr
GPIO089Gpio_Icu0ExtIsr
GPIO190Gpio_Icu1ExtIsr
GPIO291Gpio_Icu2ExtIsr
GPIO392Gpio_Icu3ExtIsr
WWDT093Wdg_Ins0RstIsr
94Wdg_Ins0IntIsr
WWDT195Wdg_Ins1RstIsr
96Wdg_Ins1IntIsr
WWDT297Wdg_Ins2RstIsr
98Wdg_Ins2IntIsr
WWDT399Wdg_Ins3RstIsr
100Wdg_Ins3IntIsr
WWDT4101Wdg_Ins4RstIsr
102Wdg_Ins4IntIsr
OTF_CRC0103Otf_Isr
CRC0104Crc_Isr
GPT0105Gpt_Ins0Ch0Is
106Gpt_Ins0Ch1Isr
107Gpt_Ins0Ch2Isr
108Gpt_Ins0Ch3Isr
GPT1109Gpt_Ins1Ch0Isr
110Gpt_Ins1Ch1Isr
111Gpt_Ins1Ch2Isr
112Gpt_Ins1Ch3Isr
GPT2113Gpt_Ins2Ch0Isr
114Gpt_Ins2Ch1Isr
115Gpt_Ins2Ch2Isr
116Gpt_Ins2Ch3Isr
GPT3117Gpt_Ins3Ch0Isr
118Gpt_Ins3Ch1Isr
119Gpt_Ins3Ch2Isr
120Gpt_Ins3Ch3Isr
GPT4121Gpt_Ins4Ch0Isr
122Gpt_Ins4Ch1Isr
123Gpt_Ins4Ch2Isr
124Gpt_Ins4Ch3Isr
GPT5125Gpt_Ins5Ch0Isr
126Gpt_Ins5Ch1Isr
127Gpt_Ins5Ch2Isr
128Gpt_Ins5Ch3Isr
GPT6129Gpt_Ins6Ch0Isr
130Gpt_Ins6Ch1Isr
131Gpt_Ins6Ch2Isr
132Gpt_Ins6Ch3Isr
GPT7133Gpt_Ins7Ch0Isr
134Gpt_Ins7Ch1Isr
135Gpt_Ins7Ch2Isr
136Gpt_Ins7Ch3Isr
GPT8137Gpt_Ins8Ch0Isr
138Gpt_Ins8Ch1Isr
139Gpt_Ins8Ch2Isr
140Gpt_Ins8Ch3Isr
GPT9141Gpt_Ins9Ch0Isr
142Gpt_Ins9Ch1Isr
143Gpt_Ins9Ch2Isr
144Gpt_Ins9Ch3Isr
PMU145Pmu_ReqDeny0Isr
BIFSPI146Bif_SpiIsr
PVT147Pvt_McuAlarmIsr
L1FCHM(RFCHM)148Fchm_MissionIntIsr
149Fchm_NcfIntIsr
150Fchm_CfIntIsr
CMM0151Cmm_Ins0Isr
CMM1152Cmm_Ins1Isr
CMM2153Cmm_Ins2Isr
PWM0154Pwm_Generic0Isr
PWM1155Pwm_Generic1Isr
PWM2156Pwm_Generic2Isr
XSPI157Xspi_Isr
CAN0158Can0_TimestampIsr
159Can0_WakeupIsr
160Can0_ErrorIsr
161Can0_DataIsr
CAN1162Can1_TimestampIsr
163Can1_WakeupIsr
164Can1_ErrorIsr
165Can1_DataIsr
CAN2166Can2_TimestampIsr
167Can2_WakeupIsr
168Can2_ErrorIsr
169Can2_DataIsr
CAN3170Can3_TimestampIsr
171Can3_WakeupIsr
172Can3_ErrorIsr
173Can3_DataIsr
CAN4174Can4_TimestampIsr
175Can4_WakeupIsr
176Can4_ErrorIsr
177Can4_DataIsr
CAN5178Can5_TimestampIsr
179Can5_WakeupIsr
180Can5_ErrorIsr
181Can5_DataIsr
CAN6182Can6_TimestampIsr
183Can6_WakeupIsr
184Can6_ErrorIsr
185Can6_DataIsr
CAN7186Can7_TimestampIsr
187Can7_WakeupIsr
188Can7_ErrorIsr
189Can7_DataIsr
CAN8190Can8_TimestampIsr
191Can8_WakeupIsr
192Can8_ErrorIsr
193Can8_DataIsr
CAN9194Can9_TimestampIsr
195Can9_WakeupIsr
196Can9_ErrorIsr
197Can9_DataIsr
CAN10198Can10_TimestampIsr
199Can10_WakeupIsr
200Can10_ErrorIsr
201Can10_DataIsr
CAN11202Can11_TimestampIsr
203Can11_WakeupIsr
204Can11_ErrorIsr
205Can11_DataIsr
CAN12206Can12_TimestampIsr
207Can12_WakeupIsr
208Can12_ErrorIsr
209Can12_DataIsr
CAN13210Can13_TimestampIsr
211Can13_WakeupIsr
212Can13_ErrorIsr
213Can13_DataIsr
CAN14214Can14_TimestampIsr
215Can14_WakeupIsr
216Can14_ErrorIsr
217Can14_DataIsr
CAN15218Can15_TimestampIsr
219Can15_WakeupIsr
220Can15_ErrorIsr
221Can15_DataIsr
MCU ETH222Gmac_TxCh0Isr
223Gmac_TxCh1Isr
224Gmac_TxCh2Isr
225Gmac_TxCh3Isr
226Gmac_TxCh4Isr
227Gmac_TxCh5Isr
228Gmac_TxCh6Isr
229Gmac_TxCh7Isr
230Gmac_RxCh0Isr
231Gmac_RxCh1Isr
232Gmac_RxCh2Isr
233Gmac_RxCh3Isr
234Gmac_RxCh4Isr
235Gmac_RxCh5Isr
236Gmac_RxCh6Isr
237Gmac_RxCh7Isr
238Gmac_SbdIsr
239Gmac_PmtIsr
240Gmac_LpiIsr
LIN0241Lin0_Isr
LIN1242Lin1_Isr
LIN2243Lin2_Isr
LIN3244Lin3_Isr
LIN4245Lin4_Isr
LIN5246Lin5_Isr
LIN6247Lin6_Isr
LIN7248Lin7_Isr
SPI0249Spi0_Isr
SPI1250Spi1_Isr
SPI2251Spi2_Isr
SPI3252Spi3_Isr
SPI4253Spi4_Isr
SPI5254Spi5_Isr
SPI6255Spi6_Isr
SPI7256Spi7_Isr
SPI8257Spi8_Isr
SPI9258Spi9_Isr
IPC0259Ipc0_Ch0Isr
260Ipc0_Ch1Isr
261Ipc0_Ch2Isr
262Ipc0_Ch3Isr
263Ipc0_Ch4Isr
264Ipc0_Ch5Isr
265Ipc0_Ch6Isr
266Ipc0_Ch7Isr
267Ipc0_Ch8Isr
268Ipc0_Ch9Isr
269Ipc0_Ch10Isr
270Ipc0_Ch11Isr
271Ipc0_Ch12Isr
272Ipc0_Ch13Isr
273Ipc0_Ch14Isr
274Ipc0_Ch15Isr
275Ipc0_Ch16Isr
276Ipc0_Ch17Isr
277Ipc0_Ch18Isr
278Ipc0_Ch19Isr
279Ipc0_Ch20Isr
280Ipc0_Ch21Isr
281Ipc0_Ch22Isr
282Ipc0_Ch23Isr
IPC1283Ipc1_Ch0Isr
284Ipc1_Ch1Isr
285Ipc1_Ch2Isr
286Ipc1_Ch3Isr
287Ipc1_Ch4Isr
288Ipc1_Ch5Isr
289Ipc1_Ch6Isr
290Ipc1_Ch7Isr
291Ipc1_Ch8Isr
292Ipc1_Ch9Isr
293Ipc1_Ch10Isr
294Ipc1_Ch11Isr
295Ipc1_Ch12Isr
296Ipc1_Ch13Isr
297Ipc1_Ch14Isr
298Ipc1_Ch15Isr
IPC2299Ipc2_Ch0Isr
300Ipc2_Ch1Isr
301Ipc2_Ch2Isr
302Ipc2_Ch3Isr
303Ipc2_Ch4Isr
304Ipc2_Ch5Isr
305Ipc2_Ch6Isr
306Ipc2_Ch7Isr
307Ipc2_Ch8Isr
308Ipc2_Ch9Isr
309Ipc2_Ch10Isr
310Ipc2_Ch11Isr
311Ipc2_Ch12Isr
312Ipc2_Ch13Isr
313Ipc2_Ch14Isr
314Ipc2_Ch15Isr
MDMA0315Mdma0_CmnIsr
316Mdma0_Ch0Isr
317Mdma0_Ch1Isr
MDMA1318Mdma1_CmnIsr
319Mdma1_Ch0Isr
320Mdma1_Ch1Isr
321Mdma1_Ch2Isr
322Mdma1_Ch3Isr
MDMA2323Mdma2_CmnIsr
324Mdma2_Ch0Isr
325Mdma2_Ch1Isr
326Mdma2_Ch2Isr
327Mdma2_Ch3Isr
PDMA0328Pdma0_Ch0Isr
329Pdma0_Ch1Isr
330Pdma0_Ch2Isr
331Pdma0_Ch3Isr
332Pdma0_Ch4Isr
333Pdma0_Ch5Isr
PMC0334Pmc0_Isr
PMC1335Pmc1_Isr
PMC2336Pmc2_Isr
GM_TRANS337Gm_TransIsr
AON_RTC_TRIGGER338Aon_RtcTrigIsr
PPS_IN0340Pps_Icu0Isr
PPS_IN1341Pps_Icu1Isr
PPS_IN2342Pps_Icu2Isr
PCIE_ETH344Pcie_EthPps0Isr
345Pcie_EthPps1Isr
346Pcie_EthPps2Isr
347Pcie_EthPps3Isr
INT_ROUTER_SEL289348
INT_ROUTER_SEL290349
INT_ROUTER_SEL291350
INT_ROUTER_SEL292351
INT_ROUTER_SEL293352
INT_ROUTER_SEL294353
HSM_IPC2354Ipc_HsmIpc2Ch4Isr
355Ipc_HsmIpc2Ch5Isr
356Ipc_HsmIpc2Ch6Isr
357Ipc_HsmIpc2Ch7Isr
HSM_IPC1358Ipc_HsmIpc1Ch4Isr
359Ipc_HsmIpc1Ch5Isr
360Ipc_HsmIpc1Ch6Isr
361Ipc_HsmIpc1Ch7Isr
HSM_IPC0362Ipc_HsmIpc0Ch4Isr
363Ipc_HsmIpc0Ch5Isr
364Ipc_HsmIpc0Ch6Isr
365Ipc_HsmIpc0Ch7Isr
HSM_IPC3366Ipc_HsmIpc3Ch4Isr
367Ipc_HsmIpc3Ch5Isr
368Ipc_HsmIpc3Ch6Isr
369Ipc_HsmIpc3Ch7Isr
AON370Aon_PerimIsr
371Aon_GpioIsr
372Aon_WakeGpioIsr
373Aon_RtcIsr
BPU374Bpu0_Vm0Isr
375Bpu0_Vm1Isr
376Bpu0_HypIsr
377Bpu0_PvtRepIsr
378Bpu0_ClkMonIsr
379Bpu0_PvtcIsr
380Bpu1_Vm0Isr
381Bpu1_Vm1Isr
382Bpu1_HypIsr
383Bpu1_PvtRepIsr
384Bpu1_ClkMonIsr
385Bpu1_PvtcIsr
386Bpu2_Vm0Isr
387Bpu2_Vm1Isr
388Bpu2_HypIsr
389Bpu2_PvtRepIsr
390Bpu2_ClkMonIsr
391Bpu2_PvtcIsr
392Bpu3_Vm0Isr
393Bpu3_Vm1Isr
394Bpu3_HypIsr
395Bpu3_PvtRepIsr
396Bpu3_ClkMonIsr
397Bpu3_PvtcIsr
398Cam_Cpe0CmmIsr
399Cam_Cpe1CmmIsr
400Cam_Cpe2CmmIsr
401Cam_Cpe3CmmIsr
402Cam_CpeLiteCmmIsr
403Cam_IdeCmmIsr
404Cam_TopCmmIsr
CPU_IPC2_CH0405Ipc_CpuIpc2Ch0Isr
CPU_IPC2_CH1406Ipc_CpuIpc2Ch1Isr
CPU_IPC2_CH2407Ipc_CpuIpc2Ch2Isr
CPU_IPC2_CH3408Ipc_CpuIpc2Ch3Isr
CPU_IPC2_CH4409Ipc_CpuIpc2Ch4Isr
CPU_IPC2_CH5410Ipc_CpuIpc2Ch5Isr
CPU_IPC2_CH6411Ipc_CpuIpc2Ch6Isr
CPU_IPC2_CH7412Ipc_CpuIpc2Ch7Isr
CPU_IPC3_CH0413Ipc_CpuIpc3Ch0Isr
CPU_IPC3_CH1414Ipc_CpuIpc3Ch1Isr
CPU_IPC3_CH2415Ipc_CpuIpc3Ch2Isr
CPU_IPC3_CH3416Ipc_CpuIpc3Ch3Isr
CPU_IPC3_CH4417Ipc_CpuIpc3Ch4Isr
CPU_IPC3_CH5418Ipc_CpuIpc3Ch5Isr
CPU_IPC3_CH6419Ipc_CpuIpc3Ch6Isr
CPU_IPC3_CH7420Ipc_CpuIpc3Ch7Isr
CPU_IPC4_CH0421Ipc_CpuIpc4Ch0Isr
CPU_IPC4_CH1422Ipc_CpuIpc4Ch1Isr
CPU_IPC4_CH2423Ipc_CpuIpc4Ch2Isr
CPU_IPC4_CH3424Ipc_CpuIpc4Ch3Isr
CPU_IPC5_CH0425Ipc_CpuIpc5Ch0Isr
CPU_IPC5_CH1426Ipc_CpuIpc5Ch1Isr
CPU_IPC5_CH2427Ipc_CpuIpc5Ch2Isr
CPU_IPC5_CH3428Ipc_CpuIpc5Ch3Isr
CPU_IPC6_CH0429Ipc_CpuIpc6Ch0Isr
CPU_IPC6_CH1430Ipc_CpuIpc6Ch1Isr
CPU_IPC6_CH2431Ipc_CpuIpc6Ch2Isr
CPU_IPC6_CH3432Ipc_CpuIpc6Ch3Isr
CPU_IPC7_CH0433Ipc_CpuIpc7Ch0Isr
CPU_IPC7_CH1434Ipc_CpuIpc7Ch1Isr
CPU_IPC7_CH2435Ipc_CpuIpc7Ch2Isr
CPU_IPC7_CH3436Ipc_CpuIpc7Ch3Isr
437CpuMp2_CmmTopIsr
438CpuMp2_Power0Isr
439CpuMp2_Power1Isr
440CpuMp2_CmmIsr
441CpuMp4_0_CmmTopIsr
442CpuMp4_0_Power0Isr
443CpuMp4_0_Power1Isr
444CpuMp4_0_CmmIsr
445CpuMp4_1_CmmTopIsr
446CpuMp4_1_Power0Isr
447CpuMp4_1_Power1Isr
448CpuMp4_1_CmmIsr
449CpuMp4_2_CmmTopIsr
450CpuMp4_2_Power0Isr
451CpuMp4_2_Power1Isr
452CpuMp4_2_CmmIsr
453CpuMp4_3_CmmTopIsr
454CpuMp4_3_Power0Isr
455CpuMp4_3_Power1Isr
456CpuMp4_3_CmmIsr
457Gpu_CmmTopIsr
458Hsi_Cmm1Isr
459Hsi_Cmm0Isr
460l20_SramIsr
461l21_SramIsr
462l22_SramIsr
463l23_SramIsr
464MediaBot_CmmIsr
465MediaBot_Ddr2CmmIsr
466MediaBot_Ddr3CmmIsr
467MediaBot_DdrWrap1MainCmmIsr
468MediaBot_DdrWrap1CmmIsr
469MediaBot_DdrWrap1PvtIsr
470MediaBot_Ddr6CmmIsr
471MediaBot_Ddr7CmmIsr
472MediaBot_DdrWrap3MainCmmIsr
473MediaBot_DdrWrap3CmmIsr
474MediaBot_DdrWrap3PvtIsr
475MediaBot_Ddr0CmmIsr
476MediaBot_Ddr1CmmIsr
477MediaBot_DdrWrap0MainCmmIsr
478MediaBot_DdrWrap0CmmIsr
479MediaBot_DdrWrap0PvtIsr
480MediaBot_Ddr4CmmIsr
481MediaBot_Ddr5CmmIsr
482MediaBot_DdrWrap2MainCmmIsr
483MediaBot_DdrWrap2CmmIsr
484MediaBot_DdrWrap2PvtIsr
485MediaTop_CmmIsr
486MediaTop_Cmn0Isr
487MediaTop_Cmn1Isr
488MediaTop_Cmn2Isr
489MediaTop_Cmn3Isr
490MediaTop_Cmn4Isr
491MediaTop_Cmn5Isr
492MediaTop_Cmn6Isr
493MediaTop_Cmn7Isr
494MediaTop_Cmn8Isr
495MediaTop_Cmn9Isr
496MediaTop_Cmn10Isr
497MediaTop_Cmn11Isr
498MediaTop_Cmn12Isr
499MediaTop_Cmn13Isr
500MediaTop_Cmn14Isr
501MediaTop_Cmn15Isr
502Peri_UsbIsr
503Peri_Cmm0Isr
504Vdsp0_CmmTopIsr
505Vdsp1_CmmTopIsr
506Video_Wrap0Isr
507Video_Wrap1Isr
508Video_Wrap2Isr
509Video_Jpu0
510Video_Jpu1
511Video_Jpu2
512Video_CmmIsr
513Rec_Irq139
514Rec_Irq140
515Rec_Irq141
516Rec_Irq142
517Rec_Irq143
518Rec_Irq144
519Rec_Irq145
520Rec_Irq146
521Rec_Irq147
522Rec_Irq148
523Rec_Irq149

MCU Interrupt Usage​

Since MCU0 and MCU1 are in the same hardware domain, when an interrupt occurs, both MCU0 and MCU1 can receive the same interrupt. Therefore, to ensure the normal operation of the MCU system, the same interrupt can only be enabled by either MCU0 or MCU1. However, because MCU0 is not open-source, it is necessary to summarize the interrupts used by MCU0 to avoid conflicts during the development of MCU1 customers.

Currently, MCU0 has used the following interrupts:

ModuleInterrupt NumberName
GPIO068Gpio_Icu0ExtIsr
GPIO169Gpio_Icu1ExtIsr
GPIO270Gpio_Icu2ExtIsr
WWDT071Wdg_Ins0RstIsr
WWDT072Wdg_Ins0IntIsr
WWDT173Wdg_Ins1RstIsr
WWDT174Wdg_Ins1IntIsr
WWDT275Wdg_Ins2RstIsr
WWDT276Wdg_Ins2IntIsr
GPT081Gpt_Ins0Ch2Isr
GPT183Gpt_Ins1Ch0Isr
GPT184Gpt_Ins1Ch1Isr
L1FCHM106Fchm_MissionIntIsr
107Fchm_NcfIntIsr
108Fchm_CfIntIsr
PWM0111Pwm_Generic0Isr
MDMA1211Mdma1_Ch0Isr
PDMA0213PDMA0_Ch0Isr
PPS(RTC)221Pps_IcuRtcIsr
HSM_IPC1241Ipc_HsmIpc1Ch4Isr
HSM_IPC1242Ipc_HsmIpc1Ch5Isr
CPU_IPC1_CH0251Ipc_CpuIpc1Ch0Isr
CPU_IPC1_CH1252Ipc_CpuIpc1Ch1Isr
CPU_IPC1_CH2253Ipc_CpuIpc1Ch2Isr
CPU_IPC0_CH8262Ipc_CpuIpc0Ch8Isr
CPU_IPC0_CH9263Ipc_CpuIpc0Ch9Isr
CPU_IPC0_CH10264Ipc_CpuIpc0Ch10Isr
CPU_IPC0_CH11265Ipc_CpuIpc0Ch11Isr
CPU_IPC0_CH12266Ipc_CpuIpc0Ch12Isr
CPU_IPC0_CH13267Ipc_CpuIpc0Ch13Isr
CPU_IPC0_CH14268Ipc_CpuIpc0Ch14Isr
CPU_IPC0_CH15269Ipc_CpuIpc0Ch15Isr
CPU_ROUTER_SWTRIG1_0270Router_Swtrig1Ch0Isr
CPU_ROUTER_SWTRIG1_1271Router_Swtrig1Ch1Isr
CPU_ROUTER_SWTRIG1_2272Router_Swtrig1Ch2Isr
CPU_ROUTER_SWTRIG1_3273Router_Swtrig1Ch3Isr
RTC360Rtc_Isr
ModuleInterrupt NumberName
HSM_IPC3366Ipc_HsmIpc3Ch4Isr
HSM_IPC3367Ipc_HsmIpc3Ch5Isr
CPU_IPC2_CH0405Ipc_CpuIpc2Ch0Isr
CPU_IPC2_CH1406Ipc_CpuIpc2Ch1Isr
CPU_IPC2_CH2407Ipc_CpuIpc2Ch2Isr
CPU_IPC2_CH3408Ipc_CpuIpc2Ch3Isr
CPU_IPC2_CH4409Ipc_CpuIpc2Ch4Isr
CPU_IPC2_CH5410Ipc_CpuIpc2Ch5Isr
CPU_IPC2_CH6411Ipc_CpuIpc2Ch6Isr
CPU_IPC2_CH7412Ipc_CpuIpc2Ch7Isr
CPU_IPC3_CH0413Ipc_CpuIpc3Ch0Isr
CPU_IPC3_CH1414Ipc_CpuIpc3Ch1Isr
CPU_IPC3_CH2415Ipc_CpuIpc3Ch2Isr
CPU_IPC3_CH3416Ipc_CpuIpc3Ch3Isr
CPU_IPC3_CH4417Ipc_CpuIpc3Ch4Isr
CPU_IPC3_CH5418Ipc_CpuIpc3Ch5Isr
CPU_IPC3_CH6419Ipc_CpuIpc3Ch6Isr
CPU_IPC3_CH7420Ipc_CpuIpc3Ch7Isr
CPU_IPC4_CH0421Ipc_CpuIpc4Ch0Isr
CPU_IPC4_CH1422Ipc_CpuIpc4Ch1Isr
CPU_IPC4_CH2423Ipc_CpuIpc4Ch2Isr
CPU_IPC4_CH3424Ipc_CpuIpc4Ch3Isr
CPU_IPC5_CH0425Ipc_CpuIpc5Ch0Isr
CPU_IPC5_CH1426Ipc_CpuIpc5Ch1Isr
CPU_IPC5_CH2427Ipc_CpuIpc5Ch2Isr
CPU_IPC5_CH3428Ipc_CpuIpc5Ch3Isr
MDMA0_CH0316Mdma0_Ch0Isr
MDMA0_CH1317Mdma0_Ch1Isr
MDMA1_CH0319Mdma1_Ch0Isr
MDMA1_CH1320Mdma1_Ch1Isr
MDMA1_CH2321Mdma1_Ch2Isr
MDMA1_CH3322Mdma1_Ch3Isr
MDMA2_CH1325Mdma2_Ch1Isr
MDMA2_CH2326Mdma2_Ch2Isr
IPC0_CH1260Ipc0_Ch1Isr
IPC0_CH2261Ipc0_Ch2Isr
IPC0_CH3262Ipc0_Ch3Isr
IPC0_CH5264Ipc0_Ch5Isr
IPC0_CH6265Ipc0_Ch6Isr
IPC0_CH8267Ipc0_Ch8Isr
IPC0_CH9268Ipc0_Ch9Isr
IPC0_CH10269Ipc0_Ch10Isr
IPC0_CH11270Ipc0_Ch11Isr
IPC1_CH0283Ipc1_Ch0Isr
IPC1_CH1284Ipc1_Ch1Isr
IPC1_CH3286Ipc1_Ch3Isr
IPC1_CH4287Ipc1_Ch4Isr
IPC1_CH5288Ipc1_Ch5Isr
IPC1_CH6289Ipc1_Ch6Isr
IPC1_CH7290Ipc1_Ch7Isr
IPC2_CH0299Ipc2_Ch0Isr
IPC2_CH1300Ipc2_Ch1Isr
IPC2_CH2301Ipc2_Ch2Isr
IPC2_CH3302Ipc2_Ch3Isr
IPC2_CH4303Ipc2_Ch4Isr
IPC2_CH5304Ipc2_Ch5Isr
IPC2_CH6305Ipc2_Ch6Isr
IPC2_CH7306Ipc2_Ch7Isr

Tutorial on Adding Compilation Directories​

Brief Introduction to Scons​

Currently, the RDK-S100 mcu only supports the compilation of s100_sip_B, and uses the scons compilation method instead of Makefile. Scons is similar to Makefile. Each folder uses a Sconscript compilation file (similar to Makefile), and a top-level SConstruct file controls the overall compilation. For example, the image for MCU1 is controlled by SConstruct_Lite_FRtos_S100_sip_B.

Process for Adding Compilation Directories​

  1. Modify the mcu/Build/FreeRtos_mcu1/SConstruct_Lite_FRtos_S100_sip_B file to add/remove corresponding modules.

    For example, to add the mcu/Service/Log folder, simply add it at the appropriate location. The variable False indicates that during the build process, source files will not be copied to the compilation output directory.

  1. Add the SConscript file under the added compilation module. The SConscript file can be obtained from any already compiled module folder.

  1. Modify the mcu/Build/FreeRtos_mcu1/build_config/S600/lite-matrix-B-mcu1.yaml file to add/remove corresponding modules.

    For example, to add the mcu/Service/Log folder, simply add it at the appropriate location. Currently, Service/Platform/McalCdd/Common has an independent path, and adding this directory should be placed in the corresponding location. For any other folders, add them directly under BuildPath.

  1. Add the SConscript file under the added compilation module. The SConscript file can be obtained from any already compiled module folder.

Introduction to the MCU FreeRtos System​

The MCU has several key system functions, as shown in the figure below:

The figure above shows the relative priority of each function's tasks and the order of calls within the same task. When integrating, customers should maintain the relative priority of each function, the core they reside on, and the order of calls within the same task. The description and precautions for each function are as follows:

Power​

ScmiProcess: Placed in a high-priority task, recommended to be placed in a 2ms task. If not feasible, the maximum scheduling period should not exceed 100ms. Placing it in a task with a long scheduling period will affect startup time. Generally, the impact can be estimated using the formula: "number of scmi communications during startup × task period."

SysPower_State_Loop/SysPower_State_MainFunction: Placed in a low-priority task.

Boot​

AcoreBootProc: Placed in a low-priority task. This includes the initialization required for Acore startup. Among these is the initialization of the Housekeeping key function, Housekeeping_WriteMagicNum. If this function is not properly initialized, Acore's access to MCU registers may cause Acore exceptions.

Integration Note: Must be placed on MCU0 for processing. AcoreBoot uses flash, so flash conflict issues must be avoided. Place it in the same low-priority task as the OTA function mentioned below.

OTA​

OtaFlash_MainFunction: Placed in a low-priority task, handling OTA-related logic.

Integration Note: Must be placed on MCU0 for processing. The OTA function uses flash, IPC, and crypto functions. Flash concurrent operation conflicts must be avoided. It is recommended to place all flash-related functions in a single low-priority task for serial execution. For example, the previously mentioned AcoreBootProc is in the same low-priority task.

Sleep/Wakeup​

SysPower_McuCoreEnterLowPower: Placed in the highest priority task with the shortest cycle supported by this core.

Integration Note: This function only runs when sleep/wakeup is required. At other times, it exits quickly without causing additional overhead.

System Interrupt Description​

MCU communication with Acore/HSM relies on IPC. Interrupts involved in IPC system services can be referenced in the Introduction to IPC section. These interrupts should be configured with a higher priority than regular functional interrupts. These interrupts themselves can be configured with the same priority.

Introduction to FreeRtos System​

There are two mainstream startup methods for FreeRTOS: First, in the main function, initialize the hardware, RTOS system, and create all tasks, then start the RTOS scheduler to begin multitasking scheduling. Second, initialize the hardware and RTOS system in the main function, create a startup task, and then start the scheduler. Within the startup task, create various application tasks. After all tasks are created successfully, the startup task deletes itself. There is no strong advantage or disadvantage between the two methods. RDK-S100/RDK-S600 choose the first method.

FreeRtos System Task Creation​

Task creation is located in /mcu/Target/Target-hobot-lite-freertos-mcu1/target/FreeRtosOsHal/Task_Hal.c, as shown in the example below:

The xxx_Startup task is responsible for startup-related initialization and runs only once. FreeRtos_OsTask_SysCore_BSW_xms and FreeRtos_OsTask_SysCore_ASW_xms are periodic tasks that schedule periodically based on different xms values. These periodic tasks also handle internal work, as detailed in the previous section "Introduction to the MCU FreeRtos System."

If customers are developing independently, they can refer to the two types of examples above. They can also handle their own demos within already created tasks, as described below. Task functions are located in the /mcu/Target/Target-hobot-lite-freertos-mcu1/target/HorizonTask.c file. Take OsTask_SysCore_BSW_10ms as an example; the task periodically checks shell transaction processing:

TASK(OsTask_SysCore_BSW_10ms)
{
    #ifdef SHELL_ENABLE
        Shell_Handler();
    #endif
}

FreeRtos System Interrupt Usage​

Interrupt usage in FreeRtos is concentrated in the /mcu/Target/Target-hobot-lite-freertos/target/FreeRtosOsHal/Isr_Hal.c file.

void FreeRtos_Irq_Init(void)
{
  int interrupt_index = 0;
  for(; interrupt_index < INTERRUPT_MCU_MAX_NUM; interrupt_index++)
  {
    if((!Interrupt_McuConfigs[interrupt_index].irqNumber) && (!Interrupt_McuConfigs[interrupt_index].priority)
        && (!Interrupt_McuConfigs[interrupt_index].Handler) && (!Interrupt_McuConfigs[interrupt_index].enable_flag))
    {
      break;
    }

    if(Interrupt_McuConfigs[interrupt_index].Handler)
    {
      INT_SYS_InstallHandler(Interrupt_McuConfigs[interrupt_index].irqNumber, Interrupt_McuConfigs[interrupt_index].Handler, NULL);
    }

    if(Interrupt_McuConfigs[interrupt_index].priority)
    {
      INT_SYS_SetPriority(Interrupt_McuConfigs[interrupt_index].irqNumber, Interrupt_McuConfigs[interrupt_index].priority);
    }

    if(Interrupt_McuConfigs[interrupt_index].enable_flag)
    {
      INT_SYS_EnableIRQ(Interrupt_McuConfigs[interrupt_index].irqNumber);
    }
  }

}

If no interrupt handler is set, the interrupt handler remains in its default state, as shown in the /mcu/Target/Target-hobot-lite-freertos-mcu1/target/SuperSoC_ISR.s file. Take the RTC interrupt handler as an example:

// DefaultISR---default interrupt handler
    .align  4
    .weak   DefaultISR
    .type   DefaultISR, %function
DefaultISR:
    hlt #0
    b   .
    .pool
    .size   DefaultISR, . - DefaultISR

/*    Macro to define default handlers. Default handler
 *    will be weak symbol and just dead loops. They can be
 *    overwritten by other handlers */
    .macro  def_irq_handler handler_name
    .weak   \handler_name
    .set    \handler_name, DefaultISR
    .endm

// Set the default interrupt handler for RTC
    def_irq_handler AON_RTC_INTR

Note: When enabling interrupts on MCU1, ensure that the corresponding interrupts on MCU0 are disabled!!!

Introduction to FreeRtos Memory Management Scheme​

The FreeRtos memory management scheme is located in the /mcu/OpenSource/FreeRTOS/portable/MemMang/ folder. There are five types of memory management algorithms: heap_1.c, heap_2.c, heap_3.c, heap_4.c, and heap_5.c. FreeRTOS's memory management module manages memory allocation and deallocation for users and the system, optimizing memory utilization and efficiency while minimizing memory fragmentation issues that may arise in the system.

heap_1.c​

The heap_1.c management scheme is the simplest among all memory management schemes provided by FreeRTOS. It only allows memory allocation and not deallocation. This is ideal for safety-critical embedded devices because disallowing memory deallocation prevents memory fragmentation that could crash the system. However, it has the drawback of low memory utilization, as a segment of memory can only be used for allocation and cannot be recycled by the system even if used only once.

heap_2.c​

The heap_2.c scheme uses a different memory management algorithm than heap_1.c, employing a best-fit algorithm. For example, if you request 100 bytes of memory and there are available memory blocks of sizes 200 bytes, 500 bytes, and 1000 bytes, the algorithm's best fit would split the 200-byte block and return the starting address of the allocated memory, reinserting the remaining memory into the linked list for future requests. Heap_2.c supports freeing allocated memory and reinserting the freed memory into the linked list, sorted by size. However, it cannot merge two adjacent small memory blocks into a larger one. This approach works fine if memory allocation sizes are relatively fixed, but if allocation sizes vary, memory fragmentation can occur. The heap_4.c scheme, discussed later, addresses this issue by merging adjacent freed memory blocks into a larger block.

heap_3.c​

The heap_3.c scheme simply wraps the standard C library's malloc() and free() functions and works with common compilers. The wrapped malloc() and free() functions include protection features, suspending the scheduler before memory operations and resuming it afterward.

heap_4.c​

The heap_4.c scheme, like heap_2.c, uses the best-fit algorithm for dynamic memory allocation. However, heap_4.c also includes a merging algorithm that combines adjacent free memory blocks into a larger block, reducing memory fragmentation. heap_4.c is particularly suitable for code that can directly use pvPortMalloc() and vPortFree() functions for memory allocation and deallocation at the porting layer. The free block list in heap_4.c is not sorted by block size but by the starting address of the memory blocks, with smaller addresses first and larger addresses later. This change accommodates the merging algorithm, which merges adjacent free memory blocks if their addresses are continuous during deallocation.

heap_5.c​

The heap_5.c scheme implements dynamic memory allocation similarly to heap_4.c, using the best-fit algorithm and merging algorithm. It also allows the memory heap to span multiple non-contiguous memory regions, enabling memory allocation across non-contiguous memory heaps. For example, users can define a memory heap in on-chip RAM and one or more additional memory heaps in external SDRAM, all managed by the system. This scheme is more complex and slightly less real-time than heap_4.c.

RDK-S100 Memory Scheme​

RDK-S100 uses the heap_4.c scheme, which combines the best-fit algorithm and merging algorithm. It can allocate and deallocate random byte-sized memory, avoiding memory fragmentation while covering all scenarios of real-time system memory allocation, with good real-time performance.

RDK-S600 Memory Scheme​

RDK-S600 uses the heap_4.c scheme, which combines the best-fit algorithm and merging algorithm. It can allocate and deallocate random byte-sized memory, avoiding memory fragmentation while covering all scenarios of real-time system memory allocation, with good real-time performance.

LOG Area Adjustment​

The examples in this section are based on S100; S600 is similar.

MCU1 Area Adjustment​

Modify the corresponding location in the /mcu/Build/FreeRtos_mcu1/Linker/gcc/S100.ld file. The size is not currently modifiable.

Acore Area Adjustment​

Modify the corresponding location in the /source/hobot-drivers/kernel-dts/drobot-s100-soc.dtsi file, keeping it consistent with the MCU1 modification.

Reserved Shared Memory Area Between MCU and Acore​

This shared memory area is allocated in the MCU0 space. However, since MCU0 and MCU1 belong to the same MCU SRAM domain, MCU1 can also use the corresponding address.

MCU_STATE_Reserved      : org = 0x0C800400, len = 1K

Currently Occupied Areas:​

MCU1_VERSION:  org = 0x0C800400, len = 0x60
MCU_ALIVE:     org = 0x0C800460, len = 0x10
     ---MCU0_ALIVE：org = 0x0C800460, len = 0x04；
     ---MCU1_ALIVE：org = 0x0C800464, len = 0x04；
     ---REVERSED：  org = 0x0C800468, len = 0x08；

Usage Precautions​

If shared memory is used for data transfer, there may be an issue where MCU updates data to SRAM, but the Acore cache still contains old data, leading to data read inconsistencies.

To avoid data inconsistency between Acore and MCU, add "volatile" or the "ioremap_np() function" before the variable. Both methods avoid reading from the cache and instead read SRAM data directly.

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